In recent years, semiconductor integrated circuit elements (IC chips) used for a CPU in computers or the like operate at higher speeds with high level functional features, than previously. Along with this advance, the number of terminals has increased and the terminal interval has tended to be smaller or more narrow. Generally speaking, in such constructions, terminals in large numbers are densely formed on the bottom surface of the IC chip in an array, and a terminal block so formed is connected to a further terminal block at the motherboard side by a conventional “flip chip” connection. However, because there is a large difference in pitch between the terminal block at the IC chip side and the terminal block at the motherboard side, it is difficult to directly connect the IC chip to the motherboard. Therefore, the connection method generally employed is one wherein the IC chip is first mounted on a wiring board adapted for mounting the IC chip, and then the wiring board is mounted on the motherboard. An example of such wiring boards for mounting the IC chip includes a wiring board wherein a ceramic chip is embedded in a core substrate comprised of a polymer material so as to form a core portion, and a built-up layer is formed on both top and rear surfaces of the core portion, respectively. See, for example, Japanese Patent Application Laid-Open (kokai) No. 2005-39217 and Japanese Patent Application Laid-Open (kokai) No. 2005-39243.
A manufacturing method for the above-described conventional wiring board for mounting an IC chip will now be discussed with reference to FIGS. 18 and 19. As shown in FIG. 18, a substrate core 211 is first prepared. Substrate core 211 is comprised of a polymer material and includes a housing opening portion 214, i.e., an opening that serves as a housing, which opens at both a core top surface 212 and a core rear surface 213. Further, a ceramic chip 221 to be embedded in core 211 is prepared. Chip 221 includes a plurality of terminal electrodes 224 formed on a top surface 222 and a rear surface 223, respectively, of chip 221 so as to protrude therefrom. Next, a taping step, wherein an adhesive tape 231 is adhered to the side facing the core rear surface 213, is performed so that the opening at the side of the core rear surface 213 of the housing opening portion 214 may be sealed in advance. Then, an accommodation step for accommodating the ceramic chip 221 in the housing opening portion 214 is performed so as to temporarily fix the rear surface 223 of the ceramic chip 221 to an adhesive face 232 of the adhesive tape 231. Subsequently, a filler 241 is disposed in the gap between the inner surface of the housing opening portion 214 and the side face 225 of the ceramic chip 221, and is cured in a fixing step to thereby fix the ceramic chip 221 in the substrate core 211. After this step, a built-up layer is formed on the top and rear surfaces of the core portion, which is comprised of the substrate core 211 and the ceramic chip 221, by alternately forming (i) a plurality of interlayer insulating layers principally comprised of polymer material and (ii) a plurality of conductor layers. This completes the wiring board for mounting the IC chip.
A disadvantage of the method of FIGS. 18 and 19 is that when the above-mentioned gap is filled with filler 241, the ceramic chip 221 is likely to float from, i.e., be vertically spaced from, the adhesive face 232 of the adhesive tape 231 by the height of the terminal electrodes 224. As a result, the filler 241 may overflow onto a chip rear surface 223 of the ceramic chip 221 (as shown in FIG. 19). In particular, when the terminal electrodes 224 are not disposed in an outer circumferential portion of the ceramic chip 221, the thickness of the outer circumferential portion is thinner than that of a portion at which the terminal electrode 224 is disposed, so that an overflow of the filler 241 is likely to occur. As a result, the terminal electrodes 224 on the rear surface 223 of the ceramic chip will be covered with the filler 241, thereby causing failure of the electrical connection to a built-up layer provided at the rear surface of the above-mentioned core portion. Moreover, even when an electrical connection with the built-up layer is made, the connection may not be reliable.